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LTC2442 1 2442f v in differential (v) ?.048 ? error (ppm) ? ? ? 0 5 2 ?.024 0 2442 ta02 ? 3 4 1 1.024 2.048 v incm = 2.048v v ref = 4.096v v cc = 5v v + = 5v v = 0v 24-bit high speed 4-channel ? adc with integrated ampli er the ltc 2442 is an ultra high precision, variable speed, 24-bit ? tm adc with integrated ampli? er. the ampli? er can be con? gured as a buffer for easy input drive of high impedance sensors. 1 part-per-million (ppm) linearity is achievable when the ampli? er is con? gured in unity gain. external resistors can be used to set a gain for increased resolution of low level input signals. the positive and negative ampli? er supply pins may be tied directly to v cc (4.5v to 5.5v) and gnd or biased above v cc and below gnd for rail-to-rail input signals. the proprietary ? architecture ensures stable dc ac- curacy through continuous transparent calibration. ten speed/resolution combinations from 6.9hz/220nv rms to 3.5khz/25v rms can be selected with no latency or shift in dc accuracy. additionally, a 2x speed mode can be selected enabling output rates up to 7khz (8khz with an external oscillator) with one cycle latency. any combination of single-ended (up to 4 inputs) or dif- ferential (up to 2 inputs) can be selected with a common mode input range from ground to v cc . while operating in the 1x speed mode the ? rst conversion following a new speed/resolution or channel selection is valid. auto ranging 6-digit dvms high speed multiplexing weight scales direct temperature measurement high speed data acquisition 1ppm linearity with no missing codes integrated ampli? er for direct sensor digitization 2 differential or 4 single-ended input channels up to 8khz output rate up to 4khz multiplexing rate selectable speed/resolution 2v rms noise at 1.76khz output rate 220nv rms noise at 13.8hz output rate with simultaneous 50hz/60hz rejection guaranteed modulator stability and lock-up immunity for any input and reference conditions <5v offset (4.5v < v cc < 5.5v, C40c to 85c) differential input and differential reference with gnd to v cc common mode range no latency mode, each conversion is accurate even after a new channel is selected internal oscillatorno external components 36-lead ssop package high precision data acquisition system applicatio s u features descriptio u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. no latency ? is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6140950, 6169506, 6411242, 6639526. LTC2442 integral non-linearity sdi sck sdo cs f o v cc 4.5v to 5.5v 4.5v to 15v ?5v to 0v 0.1 f gnd v ref v ref + 2442 ta01 4-wire spi interface LTC2442 = external oscillator = internal oscillator (simultaneous 50hz/60hz rejection at 6.9hz output rate) ch0 ch1 ch2 ch3 com 0.1 f auto-cal variable speed/ resolution differential 24-bit ? adc high z 2-channel differential/ 4-channel single ended + + v + v
LTC2442 2 2442f supply voltage (v cc ) to gnd ....................... C0.3v to 6v analog input pins voltage to gnd ...................................... C0.3v to (v cc + 0.3v) reference input pins voltage to gnd ...................................... C0.3v to (v cc + 0.3v) digital input voltage to gnd ......... C0.3v to (v cc + 0.3v) digital output voltage to gnd ....... C0.3v to (v cc + 0.3v) operating temperature range LTC2442cg .................................................. 0c to 70c LTC2442ig ............................................... C40c to 85c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c ampli? er supply voltage (v + to v C ) ..........................36v (notes 1, 2) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4, 15) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref (note 5) 24 bits integral nonlinearity v cc = 5v, ref + = 5v, ref C = gnd, v incm = 2.5v (note 6, 14) v cc = 5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v (note 6, 14) ref + = 4.096v, ref C = gnd, v incm = 2.048v (note 6, 14) 2 2 1 10 7 ppm of v ref ppm of v ref ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, gnd sel + = sel C v cc (note 12) 2.5 5 v offset error drift 2.5v ref + v cc , ref C = gnd, gnd sel + = sel C v cc 20 nv/c positive full-scale error ref + = 5v, ref C = gnd, sel + = 3.75v, sel C = 1.25v ref + = 2.5v, ref C = gnd, sel + = 1.875v, sel C = 0.625v 10 10 50 50 ppm of v ref ppm of v ref positive full-scale error drift 2.5v ref + v cc , ref C = gnd, sel + = 0.75 ? ref + , sel C = 0.25 ? ref + 0.2 ppm of v ref /c electrical characteristics absolute axi u rati gs w ww u package/order i for atio uu w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 sck busy ext dgnd agnd ch0 ch1 ch2 ch3 adcinb adcina outa ?na nc nc nc outb ?nb sdo cs f o sdi gnd ref ref + v cc com muxouta muxoutb +ina v nc nc v+ nc +inb t jmax = 125c, ja = 160c/w order part number part marking LTC2442cg LTC2442ig LTC2442cg LTC2442ig order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges.
LTC2442 3 2442f symbol parameter conditions min typ max units sel + absolute/common mode sel + voltage sel + is the positive selected input channel, see table 3 gnd C 0.3 v cc + 0.3 v sel C absolute/common mode sel C voltage sel C is the negative selected input channel, see table 3 gnd C 0.3 v cc + 0.3 v v in input differential voltage range (sel + C sel C ) Cv ref /2 v ref /2 v ref + absolute/common mode ref + voltage 0.1 v cc v ref C absolute/common mode ref C voltage gnd v cc C 0.1 v v ref reference differential voltage range (ref + C ref C ) 0.1 v cc v c s(adcina) adcina sampling capacitance 2 pf c s(adcinb) adcinb sampling capacitance 2 pf c s(ref + ) ref + sampling capacitance 2 pf c s(ref C ) ref C sampling capacitance 2 pf i dc_leak(sel + , sel C , ref + , ref C ) leakage current, inputs and reference cs = v cc , sel + = gnd, sel C = gnd, ref + = 5v, ref C = gnd C15 1 15 na t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 15) a alog i put a u d refere ce uu u the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4, 15) electrical characteristics parameter conditions min typ max units negative full-scale error ref + = 5v, ref C = gnd, sel + = 1.25v, sel C = 3.75v ref + = 2.5v, ref C = gnd, sel + = 0.625v, sel C = 1.875v 10 10 50 50 ppm of v ref ppm of v ref negative full-scale error drift 2.5v ref + v cc , ref C = gnd, sel + = 0.25 ? ref + , sel C = 0.75 ? ref + 0.2 ppm of v ref /c total unadjusted error 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v (note 6) 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v (note 6) ref + = 2.5v, ref C = gnd, v incm = 1.25v (note 6) 12 12 12 ppm of v ref ppm of v ref ppm of v ref input common mode rejection dc 2.5v ref + v cc , ref C = gnd, gnd sel C = sel + v cc 120 db
LTC2442 4 2442f power require e ts w u the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3) symbol parameter conditions min typ max units v cc supply voltage 4.5 5.5 v v + ampli? er positive supply 4.5 15 v v C ampli? er negative supply C15 0 v i cc supply current ampli? ers and adc 10 13 ma the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) digital i puts a d digital outputs uu symbol parameter conditions min typ max units v ih high level input voltage cs, f o , ext, sdi 4.5v v cc 5.5v 2.5 v v il low level input voltage cs, f o , ext, sdi 4.5v v cc 5.5v 0.8 v v ih high level input voltage sck 4.5v v cc 5.5v (note 8) 2.5 v v il low level input voltage sck 4.5v v cc 5.5v (note 8) 0.8 v i in digital input current cs, f o , ext, sdi 0v v in v cc C10 10 a i in digital input current sck 0v v in v cc (note 8) C10 10 a c in digital input capacitance cs, f o , ext, sdi 10 pf c in digital input capacitance sck (note 8) 10 pf v oh high level output voltage sdo, busy i o = C800a v cc C 0.5 v v ol low level output voltage sdo, busy i o = 1.6a 0.4 v v oh high level output voltage sck i o = C800a (note 9) v cc C 0.5 v v ol low level output voltage sck i o = 1.6a (note 9) 0.4 v i oz hi-z output leakage sdo C10 10 a
LTC2442 5 2442f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 4.5v to 5.5v unless otherwise speci? ed. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = sel + C sel C , v incm = (sel + + sel C )/2. note 4: f o pin tied to gnd or to external conversion clock source with f eosc = 10mhz unless otherwise speci? ed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: the converter uses the internal oscillator. note 8: the converter is in external sck mode of operation such that the sck pin is used as a digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in hz. note 9: the converter is in internal sck mode of operation such that the sck pin is used as a digital output. in this mode of operation, the sck pin has a total equivalent load capacitance of c load = 20pf. note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in hz. note 11: the converter uses the internal oscillator. f o = 0v. note 12: guaranteed by design and test correlation. note 13: there is an internal reset that adds an additional 1s (typ) to the conversion time. note 14: in order to achieve optimum linearity, the ampli? er power positive supply input (v + ) must exceed the maximum input voltage level by 2v or greater. the negative ampli? er power supply input (v C ) must be at least 200mv below the minimum input voltage level. note 15: ampli? ers are externally compensated with 0.1f. ti i g characteristics w u the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units f eosc external oscillator frequency range 0.1 20 mhz t heo external oscillator high period 25 10000 ns t leo external oscillator low period 25 10000 ns t conv conversion time osr = 256 (sdi = 0) osr = 32768 (sdi = 1) external oscillator (notes 10, 13) 0.99 126 1.13 145 40 ? osr + 170 f eosc (khz) 1.33 170 ms ms ms f isck internal sck frequency internal oscillator (note 9) external oscillator (notes 9, 10) 0.8 0.9 f eosc /10 1mhz hz d isck internal sck duty cycle (note 9) 45 55 % f esck external sck frequency range (note 8) 20 mhz flesck external sck low period (note 8) 25 ns t hesck external sck high period (note 8) 25 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 9, 11) external oscillator (notes 9, 10) 30.9 35.3 320/f eosc 41.6 s s t dout_esck external sck 32-bit data output time (note 8) 32/f esck s t 1 cs to sdo low z (note 12) 025ns t 2 cs to sdo high z (note 12) 025ns t 3 cs to sck (note 9) 5 s t 4 cs to sck (note 8, 12) 25 ns t kqmax sck to sdo valid 25 ns t kqmin sdo hold after sck (note 5) 15 ns t 5 sck setup before cs 50 ns t 6 sck hold after cs 50 ns t 7 sdi setup before sck (note 5) 10 ns t 8 sdi hold after sck (note 5) 10 ns
LTC2442 6 2442f input voltage (v) ?.25 rejection (db) 2 6 10 0.75 2442 g02 ? ? 0 4 8 ? ? ?0 ?.75 ?.25 0.25 1.25 v cc = 5v v ref = 2.5v v in cm = 1.25 f o = gnd v + = 7v v = ?v ?0 c 25 c90 c input voltage (v) ?.5 rejection (db) 2 6 10 1.5 2442 g03 ? ? 0 4 8 ? ? ?0 ?.5 ?.5 0.5 2.5 v cc = 5v v ref = 5v v in cm = 1.25 f o = gnd v + = 7v v = ?v ?0 c 25 c 90 c v in (v) ?.5 inl error (ppm) 2 6 10 1.5 2442 g04 ? ? 0 4 8 ? ? ?0 ?.5 ?.5 0.5 2.5 v cc = 5v v = gnd f o = gnd v ref = 5v v in cm = 2.5v v + = 5v v + = 5.25v v + = 5.5v v in (v) ?.5 inl error (ppm) 2 6 10 1.5 2442 g05 ? ? 0 4 8 ? ? ?0 ?.5 ?.5 0.5 2.5 v cc = 5v v + = 5.5 f o = gnd v ref = 5v v in cm = 2.5v v = 0v v = ?v v = ?v v incm (v) 0 offset error (ppm of v ref ) 0 2.5 4 2442 g08 2.5 5.0 1 2 3 5 5.0 v cc = 5v v ref = 5v v ref + = 5v v ref = gnd sel + = sel = v incm osr = 32768 f o = gnd t a = 25 c temperature ( c) ?5 5.0 offset error ( v) ?.5 0 2.5 5.0 ?5 53565 2442 g09 95 125 v cc = 4.5v v ref = 2.5v v ref + = 2.5v v ref = gnd sel + = sel = gnd osr = 256 f o = gnd v cc = 5.5v, 5v v ref = 5v v ref + = 5v v ref = gnd sel + = sel = gnd osr = 256 f o = gnd v cc = 5v v cc = 5.5v v cc = 4.5v v cc (v) 4.5 offset error (ppm of v ref ) 0 2.5 5.3 2442 g06 2.5 5.0 4.7 4.9 5.1 5.5 5.0 v ref = 2.5v v ref + = 2.5v v ref = gnd sel + = sel = gnd osr = 32768 f o = gnd t a = 25 c integral non-linearity integral non-linearity vs temperature integral non-linearity vs temperature inl vs op amp positive supply voltage (v + ) inl vs op amp negative supply voltage (v C ) offset error vs supply voltage offset error vs conversion rate offset error vs common mode input voltage offset error vs temperature typical perfor a ce characteristics uw v in differential (v) ?.048 ? error (ppm) ? ? ? 0 5 2 ?.024 0 2442 ta02 ? 3 4 1 1.024 2.048 v incm = 2.048v v ref = 4.096v v cc = 5v v + = 5v v = 0v conversion rate (hz) 0 5.0 offset error (ppm of v ref ) 2.5 0 2.5 5.0 500 1000 1500 2000 2442 g07 2500 3000 3500 v cc = 5v v ref = 5v v ref + = 5v v ref = gnd sel + = sel = gnd f o = gnd t a = 25 c v + = 5v v = ?v
LTC2442 7 2442f pi fu ctio s uuu sck (pin 1): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as a digital output for the internal serial interface clock during the data output period. in the external serial clock operation mode, sck is used as the digital input for the external serial interface clock during the data output period. the serial clock op- eration mode is determined by the logic level applied to ext (pin 3). busy (pin 2): conversion in progress indicator. this pin is high while the conversion is in progress and goes low indicating the conversion is complete and data is ready. it remains low during the sleep and data output states. at the conclusion of the data output state, it goes high indicating a new conversion has begun. ext (pin 3): internal/external sck selection pin. this pin is used to select internal or external sck for output- ting/inputting data. if ext is tied low, the device is in the external sck mode and data is shifted out of the device under the control of a user applied serial clock. if ext is tied high, the internal serial clock mode is selected. the device generates its own sck signal and outputs this on the sck pin. a framing signal busy (pin 2) goes low indicating data is being output. gnd (pins 4, 5, 32): ground. multiple ground pins inter- nally connected for optimum ground current ? ow and v cc decoupling. connect each one of these pins to a common ground plane through a low impedance connection. all three pins must be connected to ground for proper operation. ch0 to ch3 (pins 6, 7, 8, 9): analog inputs. may be programmed for single-ended or differential mode. (see table 3) ancinb (pin 10): adc input. must tie to the ampli? er output, outb (pin 17). adcina (pin 11): adc input. must tie to the ampli? er output, outa (pin 12). outa (pin 12): ampli? er a output. must be compensated with 0.1f or greater capacitor. drives the adcina adc input (pin 11). Cina (pin 13): ampli? er a negative input. by shorting this pin to outa (pin 12) the ampli? er becomes a buffer with unity gain. alternatively, an external resistor network may be added here for gains greater than 1. nc (pins 14, 15, 16, 20, 22, 23): no connect. these pins should be left ? oating or tied to ground. outb (pin 17): ampli? er b output. must be compensated with 0.1f or greater capacitor. drives the adcinb adc input (pin 10). Cinb (pin 18): ampli? er b negative input. by shorting this pin to outb (pin 17) the ampli? er becomes a buffer with unity gain. alternatively, an external resistor network may be added here for gains greater than 1. +inb (pin 19): ampli? er b positive input. must tie to the multiplexer output muxoutb (pin 26). v + (pin 21): ampli? er positive supply voltage input. may tie to v cc or an external supply voltage up to 15v. bypass to gnd with 1f capacitor. v C (pin 24): ampli? er negative supply voltage input. may tie to gnd or an external supply voltage as low as C15v. bypass to gnd with a 1f capacitor. +ina (pin 25): ampli? er a positive input. must tie to the multiplexer output muxouta (pin 27). muxoutb (pin 26): multiplexer output. must tie to +inb ampli? er input (pin 19).
LTC2442 8 2442f muxouta (pin 27): multiplexer output. must tie to +ina ampli? er input (pin 25). com (pin 28): the common negative input (sel C ) for all single ended multiplexer con? gurations. the voltage on ch0-ch3 and com pins can have any value between gnd C0.3v to v cc +0.3v. within these limits, the two selected inputs (sel + and sel C ) provide a bipolar input range (v in = sel + C sel C ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over-range and under-range output codes. v cc (pin 29): positive supply voltage. bypass to gnd with a 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor as close to the part as possible. ref + (pin 30), ref C (pin 31): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the negative reference input, ref C , by at least 0.1v. bypass to gnd with 0.1f ceramic capacitor as close to the part as possible. sdi (pin 33): serial data input. this pin is used to select the speed, 1x or 2x mode, resolution and input channel for the next conversion cycle. at initial power up, the de- fault mode of operation is ch0-ch1, osr of 256 and 1x mode. the serial data input contains an enable bit which determines if a new channel/speed is selected. if this bit is low the following conversion remains at the same speed and selected channel. the serial data input is applied to the device under control of the serial clock (sck) during the data output cycle. the ? rst conversion following a new channel/speed is valid. f 0 (pin 34): frequency control pin. digital input that con- trols the internal conversion clock. when f 0 is connected to v cc or gnd, the converter uses its internal oscillator running at 9mhz. the conversion rate is determined by the selected osr such that t conv (ms) = 40 ? osr + 170/f osc (khz). the ? rst digital ? lter null is located at 8/t conv , 7khz at osr = 256 and 55hz (simultaneous 50hz/60hz at osr = 32768. this pin may be driven with a maximum external clock of 10.24mhz resulting in a maximum 8khz output rate (osr = 64, 2x mode). cs (pin 35): active low chip select. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this state as long as cs is high. a low-to-high transition on cs during the data output aborts the data transfer and starts a new conver- sion. sdo (pin 36): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. this signal is high while the conversion is in progress and goes low once the conversion is complete. pi fu ctio s uuu
LTC2442 9 2442f fu ctio al block diagra uu w converter operation converter operation cycle the LTC2442 is a multi-channel, high speed, ? analog- to-digital converter with an easy to use 3- or 4-wire serial interface (see figure 1). its operation is made up of three states. the converter operating cycle begins with the con- version, followed by the sleep state and ends with the data output/input (see figure 2). the 4-wire interface consists of serial data input (sdi), serial data output (sdo), serial clock (sck) and chip select (cs). the interface, timing, operation cycle and data out format is compatible with linears entire family of ? converters. initially, the LTC2442 performs a conversion. once the conversion is complete, the device enters the sleep state. the part remains in the sleep state as long as cs is high. the conversion result is held inde? nitely in a static shift register while the converter is in the sleep state. autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator serial interface gnd v cc ch0 ch1 ch2 ch3 com in + in sdo sck ref + adcinb adcina outb outa ref cs ext sdi busy f o 2442 f01 + + mux ?nb +inb muxoutb muxouta +ina ?na ampb ampa v + v 1.69k sdo 2442 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2442 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc convert sleep channel select speed select data output power up in + =ch0, in =ch1 osr=256,1x mode 2442 f02 cs = low and sck figure 2. LTC2442 state transition diagram applicatio s i for atio wu u u test circuits figure 1. functional block diagram
LTC2442 10 2442f once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result while operating in the 1x mode. the data output corresponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. in either scenario, the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs, sck and ext pins, the LTC2442 offers several ? exible modes of operation (internal or external sck). these various modes do not require programming con? guration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. ease of use the LTC2442 data output has no latency, ? lter settling delay or redundant data associated with the conversion cycle while operating in the 1x mode. there is a one-to-one cor- respondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. speed/resolution adjustments may be made seamlessly between two conversions without settling errors. the LTC2442 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the LTC2442 automatically enters an internal reset state when the power supply voltage v cc drops below ap- proximately 2.2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection. when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 0.5ms. the por signal clears all internal registers. the conversion im- mediately following a por is performed on the input channel sel + = ch0, sel C = ch1 at an osr = 256 in the 1x mode. following the por signal, the LTC2442 starts a normal conversion cycle and follows the succession of states described above. the ? rst conversion result fol- lowing por is accurate within the speci? cations of the device if the power supply voltage is restored within the operating range (4.5v to 5.5v) before the end of the por time interval. applicatio s i for atio wu u u msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 2442 f03 sig bit 29 ? bit 30 eoc hi-z cs sck sdi sdo busy bit 31 1 0 en sgl a2 a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 figure 3. sdi speed/resolution, channel selection, and data output timing
LTC2442 11 2442f reference voltage range the LTC2442 ? converter accepts a truly differential external reference voltage. the absolute/common mode voltage speci? cation for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the LTC2442 can accept a differential reference voltage from 0.1v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. a decrease in reference voltage will not signi? - cantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the converters overall inl performance. input voltage range the analog input is truly differential with an absolute/com- mon mode range for the ch0-ch3 and com input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the LTC2442 converts the bipolar differential input signal, v in = sel + C sel C , from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. output data format the LTC2442 serial output data stream is 32 bits long. the ? rst three bits represent status information indicating the sign and conversion state. the next 24 bits are the conversion result, msb ? rst. the remaining ? ve bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. in the case of ultrahigh resolution modes, more than 24 effective bits of performance are possible (see table 4). under these conditions, sub lsbs are included in the conversion result and represent useful information beyond the 24-bit level. the third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). bit 31 (? rst output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indicator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most signi? cant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. LTC2442 status bits input range bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb v in 0.5 ? v ref 001 1 0v v in < 0.5 ? v ref 001 0 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C0.5 ? v ref 000 0 bits 28-5 are the 24-bit conversion result msb ? rst. bit 5 is the least signi? cant bit (lsb). bits 4-0 are sub lsbs below the 24-bit level. bits 4-0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and sck is ignored. in order to shift the conversion result out of the device, cs must ? rst be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the ? rst rising edge of sck. bit 30 is shifted out of the device on applicatio s i for atio wu u u
LTC2442 12 2442f the ? rst falling edge of sck. the ? nal data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the sel + and sel C pins is main- tained within the C0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. serial interface pins the LTC2442 transmits the conversion result and receives the start of conversion command through a synchronous 3- or 4-wire interface. during the conversion and sleep states, this interface can be used to access the converter status and during the data output state it is used to read the conversion result and program the speed, resolution and input channel. serial clock input/output (sck) the serial clock signal present on sck (pin 1) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the LTC2442 creates its own serial clock. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected by tying ext (pin 3) low for external sck and high for internal sck. serial data output (sdo) the serial data output pin, sdo (pin 36), provides the result of the last conversion as a serial bit stream (msb ? rst) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 35) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the ? rst rising edge of sck occurs while cs = low. applicatio s i for atio wu u u table 2. LTC2442 output data format differential input voltage v in * bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb bit 27 bit 26 bit 25 ... bit 0 v in * 0.5 ? v ref ** 0011000...0 0.5 ? v ref ** C1lsb 0010111...1 0.25 ? v ref ** 0010100...0 0.25 ? v ref ** C1lsb 0010011...1 0 0010000...0 C1lsb 0001111...1 C0.25 ? v ref ** 0001100...0 C0.25 ? v ref ** C1lsb 0001011...1 C0.5 ? v ref ** 0001000...0 v in * < C0.5 ? v ref ** 0000111...1 *the differential input voltage v in = sel + C sel C . **the differential reference voltage v ref = ref + C ref C .
LTC2442 13 2442f table 3. channel selection mux address channel selection sgl odd/sign a2 a1 a0 ch0 ch1 ch2 ch3 com 00000sel + sel C 00001 sel + sel C 01000sel C sel + 01001 sel C sel + 10000sel + sel C 10001 sel + sel C 11000 sel + sel C 11001 sel + sel C table 4. speed/resolution selection osr3 osr2 osr1 osr0 twox conversion rate rms noise enob osr latency internal 9mhz clock external 10.24mhz clock 0 0 0 0 0 keep previous speed/resolution 0 0 0 1 0 3.52khz 4khz 23v 17.7 64 none 0 0 1 0 0 1.76khz 2khz 36v 20.4 128 none 0 0 1 1 0 879hz 1khz 2.1v 21.2 256 none 0 1 0 0 0 439hz 500hz 1.5v 21.6 512 none 0 1 0 1 0 220hz 250hz 1.2v 22 1024 none 0 1 1 0 0 110hz 125hz 840nv 22.5 2048 none 0 1 1 1 0 55hz 62.5hz 630nv 22.9 4096 none 1 0 0 0 0 27.5hz 31.25hz 430nv 23.5 8192 none 1 0 0 1 0 13.73hz 15.625hz 305nv 24 16384 none 1 1 1 1 0 6.875hz 7.8125hz 220nv 24.4 32768 none 0 0 0 0 1 keep previous speed/resolution 0 0 0 1 1 7.03khz 8khz 23v 17.7 64 1 cycle 0 0 1 0 1 3.52khz 4khz 3.6v 20.4 128 1 cycle 0 0 1 1 1 1.76khz 2khz 2.1v 21.2 256 1 cycle 0 1 0 0 1 879hz 1khz 1.5v 21.6 512 1 cycle 0 1 0 1 1 439hz 500hz 1.2v 22 1024 1 cycle 0 1 1 0 1 220hz 250hz 840nv 22.5 2048 1 cycle 0 1 1 1 1 110hz 125hz 630nv 22.9 4096 1 cycle 1 0 0 0 1 55hz 62.5hz 430nv 23.5 8192 1 cycle 1 0 0 1 1 27.5hz 31.25hz 305nv 24 16384 1 cycle 1 1 1 1 1 13.73hz 15.625hz 220nv 24.4 32768 1 cycle applicatio s i for atio wu u u
LTC2442 14 2442f chip select input (cs) the active low chip select, cs (pin 35), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the LTC2442 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state. serial data input (sdi) the serial data input (sdi, pin 33) is used to select the speed/resolution and input channel of the LTC2442. sdi is programmed by a serial input data stream under the control of sck during the data output cycle, see figure 3. initially, after powering up, the device performs a conver- sion with sel + = ch0, sel C = ch1, osr = 256 (output rate nominally 879hz), and 1x speedup mode (no latency). once this ? rst conversion is complete, the device enters the sleep state and is ready to output the conversion result and receive the serial data input stream program- ming the speed/resolution and input channel for the next conversion. at the conclusion of each conversion cycle, the device enters this state. in order to change the speed/resolution or input channel, the ? rst three bits shifted into the device are 101. this is compatible with the programming sequence of all ltc multichannel differential input ? adcs. if the sequence is set to 000 or 100, the following input data is ignored (dont care) and the previously selected speed/resolution and channel remain valid for the next conversion. combi- nations other than 101, 100, and 000 of the three control bits should be avoided. if the ? rst three bits shifted into the device are 101, then the following ? ve bits select the input channel for the fol- lowing conversion (see tables 3 and 4). the next ? ve bits select the speed/resolution and mode 1x (no latency) 2x (double output rate with one conversion latency), see table 4. if these ? ve bits are set to all 0s, the previous speed remains selected for the next conversion. this is useful in applications requiring a ? xed output rate/resolution but need to change the input channel. when an update operation is initiated the ? rst three bits are 101. the following ? ve bits are the channel address. the ? rst bit, sgl, determines if the input selection is dif- ferential (sgl = 0) or single-ended (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a dif- ferential input. for sgl = 1, one of 4 channels is selected as the positive input. the negative input is com for all single ended operations. the next 4-bits (odd, a2, a1, a0) determine which channel is selected and its polarity, (see table 3). in order to remain software compatible with ltcs other multi-channel ? adcs, a2 and a1 are unused and should be set low. speed multiplier mode in addition to selecting the speed/resolution, a speed multiplier mode is used to double the output rate while maintaining the selected resolution. the last bit of the 5-bit speed/resolution control word (twox, see table 4) determines if the output rate is 1x (no speed increase) or 2x (double the selected speed). while operating in the 1x mode, the device combines two internal conversions for each conversion result in order to remove the adc offset. every conversion cycle, the offset and offset drift are transparently calibrated greatly simplifying the user interface. the resulting conversion result has no latency. the ? rst conversion following a newly applicatio s i for atio wu u u
LTC2442 15 2442f selected speed/resolution and input channel is valid. this is identical to the operation of the ltc2440 and ltc2444 through ltc2449. while operating in the 2x mode, the device performs a running average of the last two conversion results. this automatically removes the offset and drift of the device while increasing the output rate by 2x. the resolution (noise) remains the same. if a new channel is selected, the conversion result is valid for all conversions after the ? rst conversion (one cycle latency). if a new speed/resolu- tion is selected, the ? rst conversion result is valid but the resolution (noise) is a function of the running average. all subsequent conversion results are valid. if the mode is changed from either 1x to 2x or 2x to 1x without changing the resolution or channel, the ? rst conversion result is valid. the 2x mode can also be used to increase the settling time of the ampli? er between readings. while operating in the 2x mode, the multiplexer output (input to the buf- fer/ampli? er) is switched at the end of each conversion cycle. prior to concluding the data out/in cycle, the analog multiplexer output is switched. this occurs at the end of the conversion cycle (just prior to the data output cycle) for auto calibration. the time required to read the con- version enables more settling time for the ampli? er. the offset/offset drift of the ampli? er is automatically removed by the converters auto calibration sequence for both the 1x and 2x speed modes. while operating in the 1x mode, if a new input channel is selected the multiplexer is switched on the falling edge of the 14th sck (once the complete data input word is programmed). the remaining data output sequence time can be used to allow the external ampli? er to settle. busy the busy output (pin 2) is used to monitor the state of conversion, data output and sleep cycle. while the part is converting, the busy pin is high. once the conversion is complete, busy goes low indicating the conversion is complete and data out is ready. the part now enters the sleep state. busy remains low while data is shifted out of the device and sdi is shifted into the device. it goes high at the conclusion of the data input/output cycle indicating a new conversion has begun. this rising edge may be used to ? ag the completion of the data read cycle. serial interface timing modes the LTC2442s 3- or 4-wire interface is spi and microwire compatible. this interface offers several ? exible modes of operation. these include internal/external serial clock, 3- or 4-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. refer to table 5 for a summary. applicatio s i for atio wu u u table 5. interface timing modes con? guration sck source conversion cycle control data output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 4, 5 external sck, 2-wire i/o external sck sck figure 6 internal sck, single cycle conversion internal cs cs figures 7, 8 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 9
LTC2442 16 2442f external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 4. the serial clock mode is selected by the ext pin. to select the external serial clock mode, ext must be tied low. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 (busy = 1) while a conversion is in progress and eoc = 0 (busy = 0) if the device is in the sleep state. independent of cs, the device automatically enters the sleep state once the conversion is complete. when the device is in the sleep state (eoc = 0), its conver- sion result is held in an internal static shift register. the device remains in the sleep state until the ? rst rising edge of sck is seen. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the ? rst rising edge of sck and the last bit of the con- version result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) and busy goes high indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z and busy monitored for the completion of a conversion. applicatio s i for atio wu u u msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 2442 f04 sig bit 29 ? bit 30 eoc hi-z cs sck (external) sdi sdo busy bit 31 1 0 en sgl 0 0 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 conversion sleep data output conversion test eoc test eoc v cc v + +ina muxouta busy sdo sdi ext sck f o muxoutb +inb gnd 21 6 7 8 9 28 12 13 11 17 18 10 26 25 4, 5, 32 19 27 2 34 reference voltage 0.1v to v cc analog inputs 24 = external oscillator = internal oscillator (simultaneous 50hz/60hz rejection at 6.9hz output rate 1 f 0.1 f 4.5v to 5.5v v cc to 15v LTC2442 1 f 0.1 f cs 4-wire spi interface ?5v to gnd v ref + ref outb ?nb adcinb outa ?na adcina ch0 ch1 ch2 ch3 com 29 30 31 3 33 1 36 35 figure 4. external serial clock, single cycle operation
LTC2442 17 2442f as described above, cs may be pulled low at any time in order to monitor the conversion status on the sdo pin. typically, cs remains low during the data output state. however, the data output state may be aborted by pull- ing cs high anytime between the ? fth falling edge and the 32nd falling edge of sck, see figure 5. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. thirteen serial input data bits are required in order to properly program the speed/resolution and input channel. if the data output sequence is aborted prior to the 13th rising edge of sck, the new input data is ignored, and the previously selected speed/resolution and channel are used for the next conver- sion cycle. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. if a new channel is being programmed, the rising edge of cs must come after the 14th falling edge of sck in order to store the data input sequence. applicatio s i for atio wu u u cs sck (external) sdi sdo busy 123456 15 msb bit 28 bit 27 bit 26 bit 25 sig bit 29 ? bit 30 eoc hi-z hi-z bit 31 2442 f05 conversion sleep sleep data output data output conversion conversion test eoc don't care don't care don't care v cc v + +ina muxouta busy sdo sdi ext sck f o muxoutb +inb gnd 21 6 7 8 9 28 12 13 11 17 18 10 26 25 4, 5, 32 19 27 2 34 reference voltage 0.1v to v cc analog inputs 24 = external oscillator = internal oscillator (simultaneous 50hz/60hz rejection at 6.9hz output rate 1 f 0.1 f 4.5v to 5.5v v cc to 15v LTC2442 1 f 0.1 f cs ?5v to gnd v ref + ref outb ?nb adcinb ch0 ch1 ch2 ch3 com 29 30 31 3 33 1 36 35 outa ?na adcina 4-wire spi interface figure 5. external serial clock, reduced output data length
LTC2442 18 2442f external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an externally generated serial clock (sck) signal, see figure 6. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected by tying ext low. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. conversely, busy (pin 2) may be used to monitor the status of the conversion cycle. eoc or busy may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 (busy = 1) while the conversion is in progress and eoc = 0 (busy = 0) once the conversion enters the sleep state. on the falling edge of eoc/busy, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the ? rst rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the ? rst rising edge of sck. on the 32nd falling edge of sck, sdo and busy go high (eoc = 1) indicating a new conversion has begun. applicatio s i for atio wu u u cs sck (external) sdi sdo busy 2442 f06 conversion sleep data output conversion msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb sig bit 29 ? bit 30 eoc bit 31 1 0 en sgl 0 0 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 don't care don't care v cc v + +ina muxouta busy sdo sdi ext sck f o muxoutb +inb gnd 21 6 7 8 9 28 12 13 11 17 18 10 26 25 4, 5, 32 19 27 2 34 reference voltage 0.1v to v cc analog inputs 24 = external oscillator = internal oscillator (simultaneous 50hz/60hz rejection at 6.9hz output rate 1 f 0.1 f 4.5v to 5.5v v cc to 15v LTC2442 1 f 0.1 f cs ?5v to gnd v ref + ref outb ?nb adcinb ch0 ch1 ch2 ch3 com 29 30 31 3 33 1 36 35 outa ?na adcina 3-wire spi interface figure 6. external serial clock, cs = 0 operation (2-wire)
LTC2442 19 2442f internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 7. in order to select the internal serial clock timing mode, the ext pin must be tied high. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. alterna- tively, busy (pin 2) may be used to monitor the status of the conversion in progress. busy is high during the conversion and goes low at the conclusion. it remains low until the result is read from the device. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the sleep state, cs must be pulled high before the ? rst rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 500ns. if cs is pulled high before time t eoctest , the device remains in the sleep state. the conversion result is held in the internal static shift register. applicatio s i for atio wu u u msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 2442 f07 sig bit 29 ? bit 30 eoc hi-z cs sck sdi sdo busy bit 31 1 0 en sgl 0 0 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 conversion sleep data output conversion test eoc test eoc don't care don't care LTC2442 1 f 0.1 f cs 4-wire spi interface ?5v to gnd v ref + ref outb ?nb adcinb ch0 ch1 ch2 ch3 com 29 30 31 3 33 1 36 35 outa ?na adcina v cc figure 7. internal serial clock, single cycle operation
LTC2442 20 2442f if cs remains low longer than t eoctest , the ? rst rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle begins on this ? rst rising edge of sck and concludes after the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1), sck stays high and a new conversion starts. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the ? rst and 32nd rising edge of sck, see figure 8. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. thirteen serial input data bits are required in order to properly program the speed/resolution and input channel. if the data output sequence is aborted prior to the 13th rising edge of sck, the new input data is ignored, and the previously selected speed/resolution and channel are used for the next con- version cycle. if a new channel is being programmed, the rising edge of cs must come after the 14th falling edge of sck in order to store the data input sequence. applicatio s i for atio wu u u figure 8. internal serial clock, reduced data output length cs sck sdi sdo busy 2442 f08 conversion sleep data output conversion msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 sig bit 29 ? bit 30 eoc bit 31 1 0 en sgl 0 0 a0 osr3 osr2 osr1 osr0 twox odd 12345678910111213141532 don't care don't care v cc v + +ina muxouta busy sdo sdi ext sck f o muxoutb +inb gnd 21 6 7 8 9 28 12 13 11 17 18 10 26 25 4, 5, 32 19 27 2 34 reference voltage 0.1v to v cc analog inputs 24 = external oscillator = internal oscillator (simultaneous 50hz/60hz rejection at 6.9hz output rate 1 f 0.1 f 4.5v to 5.5v v cc to 15v LTC2442 1 f 0.1 f cs ?5v to gnd v ref + ref outb ?nb adcinb ch0 ch1 ch2 ch3 com 29 30 31 3 33 1 36 35 outa ?na adcina 4-wire spi interface v cc
LTC2442 21 2442f internal serial clock, 3-wire i/o, continuous conversion this timing mode uses a 3-wire, all output (sck and sdo) interface. the conversion result is shifted out of the device by an internally generated serial clock (sck) signal, see figure 9. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the internal serial clock mode is selected by tying ext high. during the conversion, the sck and the serial data output pin (sdo) are high (eoc = 1) and busy = 1. once the conversion is complete, sck, busy and sdo go low (eoc = 0) indicating the conversion has ? nished and the applicatio s i for atio wu u u device has entered the sleep state. the part remains in the sleep state a minimum amount of time (500ns) then immediately begins outputting data. the data output cycle begins on the ? rst rising edge of sck and ends after the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1) indicating a new conversion is in progress. sck remains high during the conversion. cs sck sdi sdo busy 2442 f09 conversion sleep data output conversion msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 sig bit 29 ? bit 30 eoc bit 31 1 0 en sgl 0 0 a0 osr3 osr2 osr1 osr0 twox odd 12345678910111213141532 don't care don't care v cc v + +ina muxouta busy sdo sdi ext sck f o muxoutb +inb gnd 21 6 7 8 9 28 12 13 11 17 18 10 26 25 4, 5, 32 19 27 2 34 reference voltage 0.1v to v cc analog inputs 24 = external oscillator = internal oscillator (simultaneous 50hz/60hz rejection at 6.9hz output rate 1 f 0.1 f 4.5v to 5.5v v cc to 15v LTC2442 1 f 0.1 f cs ?5v to gnd v ref + ref outb ?nb adcinb ch0 ch1 ch2 ch3 com 29 30 31 3 33 1 36 35 outa ?na adcina 3-wire spi interface v cc figure 9. internal serial clock, continuous operation
LTC2442 22 2442f table 6. osr vs notch frequency (f n ) (with internal oscillator running at 9mhz) osr notch (f n ) 64 28.13khz 128 14.06khz 256 7.03khz 512 3.52khz 1024 1.76khz 2048 879hz 4096 439hz 8192 220hz 16384 110hz 32768* 55hz * simultaneous 50/60hz rejection normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital ? ltering. combined with a large oversampling ratio, the LTC2442 signi? cantly simpli? es antialiasing ? lter requirements. the LTC2442s speed/resolution is determined by the oversample ratio (osr) of the on-chip digital ? lter. the osr ranges from 64 for 3.5khz output rate to 32,768 for 6.9hz (in no latency mode) output rate. the value of osr and the sample rate f s determine the ? lter characteristics of the device. the ? rst null of the digital ? lter is at f n and multiples of f n where f n = f s /osr, see figure 10 and table 6. the rejection at the frequency f n 14% is better than 80db, see figure 11. differential input signal frequency (hz) 0 ?0 ?0 0 180 2442 f10 ?0 ?00 60 120 240 ?20 ?40 ?0 normal mode rejection (db) sinc 4 envelope differential input signal frequency (hz) 47 ?40 normal mode rejection (db) ?30 ?20 ?10 ?00 51 55 59 63 2442 f11 ?0 ?0 49 53 57 61 figure 10. normal mode rejection (internal oscillator) figure 11. normal mode rejection (internal oscillator) applicatio s i for atio wu u u
LTC2442 23 2442f if f o is grounded, f s is set by the on-chip oscillator at 1.8mhz 5% (over supply and temperature variations). at an osr of 32,768, the ? rst null is at f n = 55hz and the no latency output rate is f n /8 = 6.9hz. at the maximum osr, the noise performance of the device is 220nv rms with better than 80db rejection of 50hz 2% and 60hz 2%. since the osr is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple. the ? rst multiple of f s occurs at 55hz ? 32,768 = 1.8mhz, see figure 12. the ? rst null becomes f n = 7.03khz with an osr of 256 (an output rate of 879hz) and f o grounded. while the null has shifted, the sample rate remains constant. as a result of constant modulator sampling rate, the linearity, offset and full-scale performance remains unchanged as does the ? rst multiple of f s . the sample rate f s and null f n , may also be adjusted by driving the f o pin with an external oscillator. the sample rate is f s = f eosc /5, where f eosc is the frequency of the clock applied to f o . combining a large osr with a reduced sample rate leads to notch frequencies f n near dc while maintaining simple antialiasing requirements. a 100khz clock applied to f o results in a null at 0.6hz plus all harmonics up to 20khz, see figure 13. this is useful in applications requiring digitalization of the dc component of a noisy input signal and eliminates the need of placing a 0.6hz ? lter in front of the adc. an external oscillator operating from 100khz to 20mhz can be implemented using the ltc1799 (resistor set sot-23 oscillator), see figure 14. by ? oating pin 4 (div) of the ltc1799, the output oscillator frequency is: fmhz k r osc set = ? ? ? ? ? ? 10 10 10 the normal mode rejection characteristic shown in figure 13 is achieved by applying the output of the ltc1799 (with r set = 100k) to the f o pin on the LTC2442 with osr = 32,768. applicatio s i for atio wu u u differential input signal frequency (hz) 0 ?0 ?0 0 2442 f12 ?0 ?00 1000000 2000000 ?20 1.8mhz ?40 ?0 normal mode rejection (db) rejection > 120db differential input signal frequency (hz) 0 ?0 ?0 0 8 2442 f13 ?0 ?0 246 10 ?00 ?20 ?40 normal mode rejection (db) figure 12. normal mode rejection (internal oscillator) figure 13. normal mode rejection (internal oscillator at 90khz)
LTC2442 24 2442f input bandwidth and frequency rejection the combined effect of the internal sinc 4 digital ? lter and the digital and analog autocalibration circuits determines the LTC2442 input bandwidth and rejection characteristics. the digital ? lters response can be adjusted by setting the oversample ratio (osr) through the spi interface or by supplying an external conversion clock to the f o pin. table 7 lists the properties of the LTC2442 with various combinations of oversample ratio and clock frequency. understanding these properties is the key to ? ne tuning the characteristics of the LTC2442 to the application. maximum conversion rate the maximum conversion rate is the fastest possible rate at which conversions can be performed. first notch frequency this is the ? rst notch in the sinc 4 portion of the digital ? lter and depends on the fo clock frequency and the oversample ratio. rejection at this frequency and its multiples (up to the modulator sample rate of 1.8mhz) exceeds 120db. this is 8 times the maximum conversion rate. effective noise bandwidth the LTC2442 has extremely good input noise rejection from the ? rst notch frequency all the way out to the modulator sample rate (typically 1.8mhz). effective noise bandwidth is a measure of how the adc will reject wideband input noise up to the modulator sample rate table 7 over- sample ratio (osr) *rms noise enob (v ref = 5v) maximum conversion rate first notch frequency effective noise bw C3db point (hz) internal 9mhz clock external f 0 internal 9mhz clock external f 0 internal 9mhz clock external f 0 internal 9mhz clock external f 0 64 23v 17.7 3515.6 f 0 /2560 28125 f 0 /320 3148 f 0 /5710 1696 f 0 /5310 128 3.6v 20.4 1757.8 f 0 /5120 14062.5 f 0 /640 1574 f 0 /2860 848 f 0 /10600 256 2.1v 21.2 878.9 f 0 /10240 7031.3 f 0 /1280 787 f 0 /1140 424 f 0 /21200 512 1.5v 21.6 439.5 f 0 /20480 3515.6 f 0 /2560 394 f 0 /2280 212 f 0 /42500 1024 1.2v 22 219.7 f 0 /40960 1757.8 f 0 /5120 197 f 0 /4570 106 f 0 /84900 2048 840nv 22.5 109.9 f 0 /81920 878.9 f 0 /1020 98.4 f 0 /9140 53 f 0 /170000 4096 630nv 22.4 54.9 f 0 /163840 439.5 f 0 /2050 49.2 f 0 /18300 26.5 f 0 /340000 8192 430nv 23.5 27.5 f 0 /327680 219.7 f 0 /4100 24.6 f 0 /36600 13.2 f 0 /679000 16384 305nv 24 13.7 f 0 /655360 109.9 f 0 /8190 12.4 f 0 /73100 6.6 f 0 /1358000 32768 220nv 24.4 6.9 f 0 /1310720 54.9 f 0 /16380 6.2 f 0 /146300 3.3 f 0 /2717000 *adc noise increases by approximately 2 when osr is decreased by a factor of 2 for osr 32768 to osr 256. the adc noise at osr 64 include effects from internal modulator quantization noise. applicatio s i for atio wu u u 29 2 30 1 36 6 7 35 3 2442 f14 34 4,5,32 reference voltage 0.1v to v cc analog input 0.5v ref to 0.5v ref 3-wire spi interface 4.5v to 5.5v 31 v cc busy f o ref + sck ch0 ch1 sdo gnd cs ext LTC2442 ref 1 f 0.1 f ltc1799 out div set gnd v + r set nc figure 14. simple external clock source
LTC2442 25 2442f optimizing linearity while the integrated op-amp has rail-to-rail input range, in order to achieve parts-per-million linearity performance, the input range and op-amp supply voltages must be con- sidered. input levels within 1.25v of the upper op-amp rail (v + ) begin to degrade the performance. for example (see figure 15) while operating with v + = 5.1v and absolute input voltages (v in cm + v in diff) up to 3.75v (v in cm = 2.5v and C2.5v < v in diff < 2.5v), the linearity is degraded to about 17-bits. once v + is increased to 5.25v or greater the linearity improves to 19-bits (2ppm). if the reference is reduced to 4.096v and the input common mode is v ref /2 (2.048v) the linearity performance improves to better than 1ppm with v + tied to v cc and v C tied to ground, see figure 16. input signals near ground require about 100mv headroom on the op-amp power supply in order to achieve 1ppm inl, see figure 17. optimal linearity is achieved by driving the input differentially. as seen in figure 18, a single ended input (the negative input is tied to ground) yields 18-bits (4ppm) linearity performance. in this case v C is 100mv below ground. applicatio s i for atio wu u u differential v in (v) ?.5 inl (ppm) 2 6 10 1.5 2442 f15 ? ? 0 4 8 ? ? ?0 1.5 ? 0.5 ? 0.5 1 2 0 2.5 v + = 5.1v, v = 0 v + = 5, v = 0 v + = 5, v = ? v ref = 5v v cc = 5v v incm = 2.5v v + > 5.25, v = 0, ?, ? differential v in (v) ?.048 inl (ppm) 0 2 2.048 2442 f16 ? ? ?.024 0 1.024 ?.536 ?.512 0.512 1.536 4 ? 1 ? 3 v ref = 4.096v v cc = 5v v incm = 2.048v v + = 5v, v = 0v figure 15. inl vs op-amp supply voltage figure 16. linearity vs v in differential input (v) ?.25 inl (ppm) ?.5 0 0.5 0.25 1.25 2442 f17 ? ?.5 ? ?.75 ?.25 0.75 1 1.5 2 v cc = 5v v ref = 5v v incm = 0.625v v + = 5v v = ?00mv single ended sel + , sel = 0v fixed 0 inl (ppm) 1 3 5 2 2442 f18 ? ? 0 2 4 ? ? ? 0.5 1 1.5 2.5 v cc = 5v v ref = 5v v in = v in + v in = 0v v + = 5v v = ?00mv figure 17. linearity near ground figure 18. single-ended linearity
LTC2442 26 2442f 1 5 5v ?v 9v 4 3 2442 f19 2 6 v out v cc gnd c ltc1983es6-5 shdn c + c2 4.7 f c6 4.7 f c5 2.2 f c3 2.2 f c4 2.2 f c1 4.7 f d1 bat54s applicatio s i for atio wu u u input bias current the 10na typical bias current of the buffers results in less than 1ppm (5v) error for source resistance imbalances of less than 500 . matching the resistance at the inputs cancels much of the error due to ampli? er bias current. for source resistances up to 50k, 1% resistors are ad- equate. figure 20 shows proper input resistance matching for a precision voltage divider on the ch2-3 inputs. the resistance seen by ch2 is the parallel combination of 30k and 10k or 7.5k. a 1%, 7.5k resistor at ch3 balances the resistance of the divider output. while the two input buffers will have slightly different bias currents, the autozero process applies the bias cur- rent from each buffer to both of the inputs for half of the conversion time, so the offset is equal to the average of the two bias currents multiplied by the mismatch in source resistance. figure 19. ltc1983 with another charge pump stacked onto v cc to give 9v the LTC2442 breaks new ground in high impedance input ? adcs. the input buffer is optimized to make driving the adc as easy as possible, while overcoming many of the limitations typical of integrated buffers. convenient +5v to C5v/+9v dc-dc converter if either of the signal inputs must include ground and v cc , then the ampli? er will require both a positive supply greater than the maximum input voltage and a negative supply. figure 19 shows how to derive both C5v and +9v from a single 5v supply using an ltc1983, allowing the adc inputs to extend as much as 300mv below ground and above v cc . for inputs that include ground but do not go within 1.5v of v cc , then c4, c5, c6 and d1 can be eliminated and the ampli? er positive supply can be connected to v cc .
LTC2442 27 2442f applicatio s i for atio wu u u low power operation the integrated buffers have a supply current of 1ma total, greatly reducing the total power consumption when the adc is operated at a low duty cycle. the typical approach to driving a ? adc is to use a high bandwidth ampli- ? er that settles very quickly in response to the sampling process at the adc input. the LTC2442 approach is to use an accurate, low bandwidth ampli? er that requires a load capacitor for compensation. this capacitor also serves as a charge reservoir during the sampling process, so the disturbance at the adc input is minimal. the ampli? er only supplies the average sampling current that the adc draws, which is on the order of 50a. scaling for higher input voltages the LTC2442 is ideally suited for applications with low-level, differential signal with a common mode approximately equal to mid-supply, such as strain gages and silicon micromachined sensors. other applications require scaling a high voltage signal to the range of the adc. figure 20 shows how to properly scale a bipolar, ground- referred input voltage to drive the LTC2442. first, the input must be level shifted so that it never exceeds the LTC2442 supply rails. this is commonly done with an instrumentation ampli? er or simple op-amp level shift circuit. rather than shift the analog input, the LTC2442 can run on 2.5v supplies so that ground is centered in the input range. this is equivalent to a perfect analog level shift with no degradation in accuracy. the digital signals are shifted from 0 to 5v logic to 2.5v logic by a very inexpensive 74hc4053 analog switch and the data from the LTC2442 is shifted back to 0 to 5v logic by a mmbt3904 transistor. on both inputs, precision resistor networks scale the input signal from 10v to 2.5v. ch0-1 is driven truly differen- tially for maximum linearity, typically better than 3ppm, however 3 resistors and an ltc2050hv autozero ampli? er are required. the 8.88k output resistor balances the offset associated with the LTC2442s bias current. the resistance seen by ch0 is 4.44k and the offset at ch0 is also inverted and appears at the output of the ltc2050hv. ch2 to ch3 is driven single-ended, with ch3 tied to ground. this degrades linearity slightly, but it is easier to implement than a true differential drive. in this case the resistance at ch3 should be equal to the resistance at ch2 or 7.5k. this circuit is also suitable for signals that are always positive, with the LTC2442 operating on a single 5v supply.
LTC2442 28 2442f applicatio s i for atio wu u u 30 29 21 31 7 8 6 9 28 11 13 12 17 18 12 10 13 2 1 5 3 6 35 2 2 6 6 5 5 1 3 4 1 33 2 4 36 34 3 26 27 25 19 14 15 4 4 5 32 24 ref + ref ch0 ch1 ch2 ch3 com adcinb adcina outa ?na outb ?nb cs sck sd0 sdi busy f o ext muouta muxoutb +ina +inb LTC2442 u1 gnd gnd gnd v v cc v + in gnd out trim + 2.5v 5v 0.1 c13 0.1 c8 x0 x1 y0 y1 z0 z1 inh x y z sdi cs sck a b c v cc v ee gnd 11 10 9 5v sdo 5k r21 1.8k r22 74hc4053 u4 ?.5v ?.5v ?. 5 5v ?.5v 2.5v ?v 4.7k c15 c14 0.1k 0.1 c17 0.1 c9 c10 0.1k 1k r20 r1 40k 5k r3 5k r4 r5 8.88k r10 7.5k r9 10k 30k r6 5v v in1 5v v in2 ?v ltc2050hv u2 lt1236n u3 ref + ref + ?.5v ?.5v mmbt3904 figure 20. scaling inputs for 10v range
LTC2442 29 2442f applicatio s i for atio wu u u details of the conversion and autozero process the LTC2442 performs automatic offset cancellation for each conversion. this is accomplished by taking the aver- age of two half-conversions with the inputs applied in opposite polarity. figure 21 shows a conversion on ch0 to ch1 differential at osr of 32768, in 1x mode. this chan- nel is selected by sending the appropriate con? guration word to the LTC2442 through the spi interface. on the 13 th falling clock edge, the ch0 input is applied to +ina through the multiplexer and ch1 is connected to +inb. the outputs of the ampli? ers slew during the remainder of the data i/o state and the conversion begins on the 32 nd falling clock edge. halfway through the conversion (approximately 73ms later) the multiplexer switches the ch0 input to +inb and the ch1 input to +ina. the digital ? lter subtracts the two half-conversions, which removes the offset of the ampli? ers and converter. at the end of a conversion, the multiplexer assumes that the next conversion will be on the same channel and switches back to the opposite polarity on the channel just converted. this gives extra settling time when convert- ing on one channel continuously. if a different channel is programmed, the multiplexer will switch again on the 13 th falling clock edge. outb outa busy sck cs figure 21. ampli? er outputs and cs, sck, busy during a conversion on ch0-1, osr32768. v indiff = 2.5v, v cm = 2.5v 20ms/div 2v/div 5v/div
LTC2442 30 2442f the ampli? ers take approximately 50s to settle for a full-scale input voltage. this does not affect accuracy in either 2x mode or 1x mode for osr values between 256 to 32768. however, the ampli? er settling time will cause a gain error in 1x mode for osr values between 64 to 256. this is because the mid-conversion slew time is a signi? cant portion of the total conversion time. figure 22 shows the details of a conversion in 1x mode, osr128, with a full-scale input voltage applied (v in = 2.5v, v cm = 2.5v). the previously selected channel had both inputs grounded. on the 13 th falling clock edge, the ampli? ers applicatio s i for atio wu u u figure 22. details of conversion in 1x mode, osr128 (outa and outb superimposed) figure 23. details of conversion in 2x mode, osr128 (outa and outb superimposed) begin slewing and have reached the correct voltage before the conversion begins. midway through the conversion, the multiplexer reverses the inputs. figure 23 shows operation in 2x mode. after the ? rst half-conversion is done, the multiplexer reverses. waiting 50s before beginning the next half-conversion allows the ampli? ers to settle fully. 2x mode is recommended for osr values between 64 and 128 because the ampli? ers have time to settle between half conversions. if only the 1x data rate is required, ignore every other sample. outb busy sck cs outb busy sck cs 200s/div 1v/div 5v/div 200s/div 1v/div 5v/div
LTC2442 31 2442f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u g36 ssop 0204 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 ?13.10* (.492 ?.516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12 g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640)
LTC2442 32 2442f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 1105 ? printed in usa part number description comments lt1025 micropower thermocouple cold junction compensator 80a supply current, 0.5c initial accuracy ltc1043 dual precision instrumentation switched capacitor building block precise charge, balanced switching, low power ltc2050 precision chopper stabilized op amp no external components 3v offset, 1.5v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/c drift lt1461 micropower series reference, 2.5v 0.04% max, 3ppm/c max drift lt1592 ultraprecise 16-bit softspan tm dac six programmable output ranges ltc1799 resistor set sot-23 oscillator single resistor frequency set ltc1983 100ma charge pump 5v to regulated C5v conversion ltc2053 rail-to-rail instrumentation ampli? er 10v offset with 50nv/c drift, 2.5v p-p noise 0.01hz to 10hz ltc2440 1-channel, differential input, high speed/low noise, 24-bit, no latency ? adc 2v rms noise at 880hz, 200nv rms noise at 6.9hz, 0.0005% inl, up to 3.5khz output rate related parts typical applicatio u scaling inputs for 10v range 30 29 21 31 7 8 6 9 28 11 13 12 17 18 12 10 13 2 1 5 3 6 35 2 2 6 6 5 5 1 3 4 1 33 2 4 36 34 3 26 27 25 19 14 15 4 4 5 32 24 ref + ref ch0 ch1 ch2 ch3 com adcinb adcina outa ?na outb ?nb cs sck sd0 sdi busy f o ext muouta muxoutb +ina +inb LTC2442 u1 gnd gnd gnd v v cc v + in gnd out trim + 2.5v 5v 0.1 c13 0.1 c8 x0 x1 y0 y1 z0 z1 inh x y z sdi cs sck a b c v cc v ee gnd 11 10 9 5v sdo 5k r21 1.8k r22 74hc4053 u4 ?.5v ?.5v ?.5v 5v ?.5v 2.5v ?v 4.7k c15 c14 0.1k 0.1 c17 0.1 c9 c10 0.1k 1k r20 r1 40k 5k r3 5k r4 r5 8.88k r10 7.5k r9 10k 30k r6 5v v in1 5v v in2 ?v ltc2050hv u2 lt1236n u3 ref + ref + ?.5v ?.5v mmbt3904

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